// Peripheral: SWPMI_Periph  Single Wire Protocol Master Interface SPWMI.
// Instances:
//  SWPMI1  mmap.SWPMI1_BASE
// Registers:
//  0x00 32  CR  Configuration/Control register.
//  0x04 32  BRR Bitrate register.
//  0x0C 32  ISR Interrupt and Status register.
//  0x10 32  ICR Interrupt Flag Clear register.
//  0x14 32  IER Interrupt Enable register.
//  0x18 32  RFL Receive Frame Length register.
//  0x1C 32  TDR Transmit data register.
//  0x20 32  RDR Receive data register.
//  0x24 32  OR  Option register.
// Import:
//  stm32/o/l476xx/mmap
package swpmi

// DO NOT EDIT THIS FILE. GENERATED BY stm32xgen.

const (
	RXDMA  CR = 0x01 << 0  //+ Reception DMA enable.
	TXDMA  CR = 0x01 << 1  //+ Transmission DMA enable.
	RXMODE CR = 0x01 << 2  //+ Reception buffering mode.
	TXMODE CR = 0x01 << 3  //+ Transmission buffering mode.
	LPBK   CR = 0x01 << 4  //+ Loopback mode enable.
	SWPACT CR = 0x01 << 5  //+ Single wire protocol master interface activate.
	DEACT  CR = 0x01 << 10 //+ Single wire protocol master interface deactivate.
)

const (
	RXDMAn  = 0
	TXDMAn  = 1
	RXMODEn = 2
	TXMODEn = 3
	LPBKn   = 4
	SWPACTn = 5
	DEACTn  = 10
)

const (
	BR BRR = 0x3F << 0 //+ BR[5:0] bits (Bitrate prescaler).
)

const (
	BRn = 0
)

const (
	RXBFF  ISR = 0x01 << 0  //+ Receive buffer full flag.
	TXBEF  ISR = 0x01 << 1  //+ Transmit buffer empty flag.
	RXBERF ISR = 0x01 << 2  //+ Receive CRC error flag.
	RXOVRF ISR = 0x01 << 3  //+ Receive overrun error flag.
	TXUNRF ISR = 0x01 << 4  //+ Transmit underrun error flag.
	RXNE   ISR = 0x01 << 5  //+ Receive data register not empty.
	TXE    ISR = 0x01 << 6  //+ Transmit data register empty.
	TCF    ISR = 0x01 << 7  //+ Transfer complete flag.
	SRF    ISR = 0x01 << 8  //+ Slave resume flag.
	SUSP   ISR = 0x01 << 9  //+ SUSPEND flag.
	DEACTF ISR = 0x01 << 10 //+ DEACTIVATED flag.
)

const (
	RXBFFn  = 0
	TXBEFn  = 1
	RXBERFn = 2
	RXOVRFn = 3
	TXUNRFn = 4
	RXNEn   = 5
	TXEn    = 6
	TCFn    = 7
	SRFn    = 8
	SUSPn   = 9
	DEACTFn = 10
)

const (
	CRXBFF  ICR = 0x01 << 0 //+ Clear receive buffer full flag.
	CTXBEF  ICR = 0x01 << 1 //+ Clear transmit buffer empty flag.
	CRXBERF ICR = 0x01 << 2 //+ Clear receive CRC error flag.
	CRXOVRF ICR = 0x01 << 3 //+ Clear receive overrun error flag.
	CTXUNRF ICR = 0x01 << 4 //+ Clear transmit underrun error flag.
	CTCF    ICR = 0x01 << 7 //+ Clear transfer complete flag.
	CSRF    ICR = 0x01 << 8 //+ Clear slave resume flag.
)

const (
	CRXBFFn  = 0
	CTXBEFn  = 1
	CRXBERFn = 2
	CRXOVRFn = 3
	CTXUNRFn = 4
	CTCFn    = 7
	CSRFn    = 8
)

const (
	SRIE    IER = 0x01 << 8 //+ Slave resume interrupt enable.
	TCIE    IER = 0x01 << 7 //+ Transmit complete interrupt enable.
	TIE     IER = 0x01 << 6 //+ Transmit interrupt enable.
	RIE     IER = 0x01 << 5 //+ Receive interrupt enable.
	TXUNRIE IER = 0x01 << 4 //+ Transmit underrun error interrupt enable.
	RXOVRIE IER = 0x01 << 3 //+ Receive overrun error interrupt enable.
	RXBERIE IER = 0x01 << 2 //+ Receive CRC error interrupt enable.
	TXBEIE  IER = 0x01 << 1 //+ Transmit buffer empty interrupt enable.
	RXBFIE  IER = 0x01 << 0 //+ Receive buffer full interrupt enable.
)

const (
	SRIEn    = 8
	TCIEn    = 7
	TIEn     = 6
	RIEn     = 5
	TXUNRIEn = 4
	RXOVRIEn = 3
	RXBERIEn = 2
	TXBEIEn  = 1
	RXBFIEn  = 0
)

const (
	RFL     RFL = 0x1F << 0 //+ RFL[4:0] bits (Receive Frame length).
	RFL_0_1 RFL = 0x03 << 0 //  RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.).
)

const (
	RFLn = 0
)

const (
	TD TDR = 0xFFFFFFFF << 0 //+ Transmit Data Register.
)

const (
	TDn = 0
)

const (
	RD RDR = 0xFFFFFFFF << 0 //+ Receive Data Register.
)

const (
	RDn = 0
)

const (
	TBYP  OR = 0x01 << 0 //+ SWP Transceiver Bypass.
	CLASS OR = 0x01 << 1 //+ SWP Voltage Class selection.
)

const (
	TBYPn  = 0
	CLASSn = 1
)
